The present invention pertains to improving data bus efficiency. More particularly, the present invention pertains to reducing the amount of data that is prefetched beyond what is needed by a system component (i.e., overshoot).
In a typical mid-range or high-end server system, a number of components are coupled to an Input/Output (I/O) bus, which in turn is coupled to system memory. The physical size and number of interconnected components in such systems can often lead to large latency periods when components on the I/O bus are writing data to and reading data from the system memory. As components are added this problem is exacerbated.
It is therefore desirable to have a system for improving bus efficiency and reducing latency as well as providing additional benefits.